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PMC
FEATURES
* Low Voltage Operation - Dual read VCC ranges: 2.7 V to 3.6 V or 4.5 V to 5.5 V - Program/Erase voltage: VCC - 2.7 V to 3.6 V and VPP - 11.5 V to 12.5 V * High Performance Read - 70 ns access time * Electrical Chip Erase and Byte Program Using EPROM Programmer - Maximum 20 s/byte programming - Maximum 100 ms chip erase - Do not require UV erase
Pm37LV512
512 Kbit (64K X 8) Dual-Voltage Multiple-Cycle-Programmable ROM
* Low Power Consumption - Typical 5 mA active read current - Typical 18 A CMOS standby current * Excellent Product Reliablity - Guarantee minimum 1,000 program/erase cycles - Minimum 20 years data retention * JEDEC Standard Byte-wide Flash Memory Pin-out * Industrial Standard Packaging - 32-pin PLCC - 32-pin PDIP - 32-pin VSOP
GENERAL DESCRIPTION
The Pm37LV512 is a 512 Kbit, Multiple-Cycle-Programmable Read-Only-Memory (MCP ROM) organized as 65,563 bytes of 8 bits each. The program and erase operation of device can be done on EPROM programmers by applying 3.0 Volt VCC and 12.0 Volt VPP to A9 and/or OE# pin. This eliminates the need of a UV-Source for erase operation such as EPROM device. The read operation of device can be in 2.7 Volt to 3.6 Volt or 4.5 Volt - 5.5 Volt range compatible to either 3.0 Volt or 5.0 Volt systems. The dual read operation ranges can greatly increase application flexibility for users. The device has a standard microprocessor interface as well as JEDEC single-power-supply Flash compatible pinout. For applications that do not require in-system-programming (ISP) function for firmwire upgrade, the Pm37LV512 offers a direct cost reduction path for Flash memory, i.e. Pm39LV512, without modifying the schematic and board layout of system. The Pm37LV512 is manufactured on PMC's advanced nonvolatile CMOS technology, P-FLASHTM. The device is offered in 32-pin PLCC, VSOP and PDIP packages with access time of 70 ns.
Programmable Microelectronics Corp.
1
Issue Date: Dec, 2002 Rev:1.3
PMC
CONNECTION DIAGRAMS
Pm37LV512
A12
A15
WE#
V CC
NC
NC
NC
A7 A6 A5 A4 A3 A2 A1 A0 I/O0
5 6 7 8 9 10 11 12 13 14 I/O1
4
3
2
1
32
31
30
29 28 27 26 25 24 23 22 21
A14 A13 A8 A9 A11 OE# A10 CE# I/O7
15 I/O2
16 GND
17 I/O3
18 I/O4
19 I/O5
20 I/O6
NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
V CC WE# NC A14 A13 A8 A9 A11 OE# A10 CE# I/O7 I/O6 I/O5 I/O4 I/O3
32-Pin PDIP
32-Pin PLCC
LOGIC SYMBOL
A11 A9 A8 A13 A14 NC WE# V CC NC NC A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
16 A0-A15 8 I/O0-I/O7 CE# OE# WE#
32-Pin VSOP
Programmable Microelectronics Corp.
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Issue Date: Dec, 2002 Rev: 1.3
PMC
PRODUCT ORDERING INFORMATION
Pm37LV512 -70 J C
Pm37LV512
Temperature Range C = Commercial (0C to +70C)
Package Type J = 32-pin Plastic J-Leaded Chip Carrier (32J) P = 32-pin Plastic DIP (32P) V = 32-pin Thin Small Outline Package (32V) Speed Option PMC Device Number
Part Number Pm37LV512-70JC PM37LV512-70PC Pm37LV512-70VC
tACC (ns)
P ackag e 32J
Temperature Range Commercial (0C to + 70C) Commercial (0C to + 70C) Commercial (0C to + 70C)
70
32P 32V
Programmable Microelectronics Corp.
3
Issue Date: Dec, 2002 Rev: 1.3
PMC
PIN DESCRIPTIONS
Pm37LV512
SYMBOL A 0 - A 15
TYPE INPUT
DESCRIPTION Address Inputs: For memory addresses input. Addresses are internally latched on the falling edge of WE# during a write cycle. Chip Enable: CE# goes low activates the device's internal circuitries for device operation. CE# goes high deselects the device and switches into standby mode to reduce the power consumption. Write Enable: Activate the device for write operation. WE# is active low. Output Enable: Control the device's output buffers during a read cycle. OE# is active low. Data Inputs/Outputs: Input command/data during a write cycle or output data during a read cycle. The I/O pins float to tri-state when OE# are disabled. Device Power Supply Ground No Connection
C E#
INPUT
WE# OE# I/O0 - I/O7 V CC GND NC
INPUT INPUT INPUT/ OUTPUT
Programmable Microelectronics Corp.
4
Issue Date: Dec, 2002 Rev: 1.3
PMC
BLOCK DIAGRAM
Pm37LV512
I/O0-I/O7 I/O BUFFERS
WE# CE# OE#
COMMAND REGISTER
CE,OE LOGIC
DATA LATCH
SENSE AMP
ADDRESS LATCH
Y-DECODER X-DECODER
Y-GATING MEMORY ARRAY
A0-A15
DEVICE OPERATION
READ OPERATION The access of Pm37LV512 is similar as that of EPROM or Flash Memory. To obtain data at the outputs, three control functions must be satisfied: * CE# is the chip enable and should be pulled low ( VIL ). * OE# is the output enable and should be pulled low ( VIL). * WE# is the write enable and should remains high ( VIH ). BYTE PROGRAMMING The Pm37LV512 is programmed by using an external EPROM programmer. The programming mode is activated by applying 12.0 Volt on OE# pin and VIL on CE# pin. The byte program operation is completed by asserting WE# to low for 20 s. A chip erase operation is required prior to program due to a data "0" can not be programmed back to a "1" and only erase operation can convert "0"s to "1"s. The entire chip can be programmed byte-by-byte by using the byte program algorithmm. Refer to Chart 1. Byte Programming Flowchart and Byte Program Operations AC Waveforms.
Programmable Microelectronics Corp.
CHIP ERASE The entire memory array can be erased through a chip erase operation on an external EPROM programmer. Pre-program the "1"s cells in the device is not required prior to chip erase operation. The chip erase operation is activated by applying 12.0 Volt to OE# and A9 pins while CE# pin is low. All other address and data pins are "don't care". Chip erase is completed by asserting WE# pin to low for 100 ms. The falling edge of WE# will start the chip erase operation. The device will return back to standby mode after the completion of chip erase. Refer to Chart 2. Chip Erase Flowchart and Chip Erase Operations AC Waveforms. PRODUCT IDENTIFICATION The hardware product identification mode can be used by an EPROM programmer to identify the device and manufacturer for selecting the right programming algorithm for the device. The product identification mode is activated by applying 12.0 Volt on A9 pin. For details, please see Bus Operation Modes in Table 1.
5
Issue Date: Dec, 2002 Rev: 1.3
PMC
OPERATING MODES
Table 1. Bus Operation Modes
Pm37LV512
Mode Read Chip-Erase Byte-Program Program/Erase Inhibit
C E# VIL VIL VIL X X
OE# VIL V H(1) VH X VIL or VIH X VIH
WE# VIH V IL VIL VIH X X X
A9 AIN VH AIN X X X X
ADDRESS AIN X
(2)
I/O DOUT High Z DIN High Z High Z/ DOUT High Z High Z Manufacturer Code Device Code
(3) (3)
AIN X X X X A 2 - A 15 = X , A1 = VIL, A0 = VIL A 2 - A 15 = X , A1 = VIL, A0 = VIH
Standby Output Disable
VIH X
Product Identification Hardware
VIL
VIL
VIH
VH
Notes: 1. VH = 12.0 V 0.5 V. 2. X can be VIL, VIH or addresses. 3. Manufacturer Code: 9Dh; Device Code: 9Bh
Programmable Microelectronics Corp.
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Issue Date: Dec, 2002 Rev: 1.3
PMC
DEVICE OPERATIONS FLOWCHARTS
BYTE PROGRAMMING
Pm37LV512
Start
OE# = V H
Address = First Location; Load Data
CE# = V IL
Program 20 s pulse (WE# = V IL )
OE# = V IL Yes Wait T R T Recovery Time
Last Address? No
Increment Address
Read Device
No
Compare all bytes to original data
Yes Failed Pass
Chart 1. Byte Programming Flowchart
Programmable Microelectronics Corp.
7
Issue Date: Dec, 2002 Rev: 1.3
PMC
DEVICE OPERATIONS FLOWCHARTS (CONTINUED)
CHIP ERASE
Pm37LV512
Start
A 9 = V H ; OE# = V H
CE# = V IL
Erase 100 ms pulse ( W E # = V IL )
W E # = V IH
O E # / A9 = V IL or V IH
Wait T R T Recovery Time
Read Device
No Compare all bytes to FF
Yes Fail Pass
Chart 2. Chip Erase Flowchart
Programmable Microelectronics Corp.
8
Issue Date: Dec, 2002 Rev: 1.3
PMC
ABSOLUTE MAXIMUM RATINGS (1)
Temperature Under Bias Storage Temperature Surface Mount Lead Soldering Temperature Input Voltage with Respect to Ground on All Pins except OE# and A9 pin (2) Input Voltage with Respect to Ground on OE# and A9 pin (3) All Output Voltage with Respect to Ground VCC (2)
Pm37LV512
-65C to +125C -65C to +125C 240C 3 Seconds -0.5 V to VCC + 0.5 V -0.5 V to +13.0 V -0.5 V to VCC + 0.5 V -0.5 V to +6.0 V
Notes: 1. Stresses under those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. The functional operation of the device or any other conditions under those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affected device reliability. 2. Maximum DC voltage on input or I/O pins are VCC + 0.5 V. During voltage transitioning period, input or I/O pins may overshoot to VCC + 2.0 V for a period of time up to 20 ns. Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period, input or I/O pins may undershoot GND to -2.0 V for a period of time up to 20 ns. 3. Maximum DC voltage on OE# and A9 pin is +13.0 V. During voltage transitioning period, OE# and A9 pin may overshoot to +14.0 V for a period of time up to 20 ns. Minimum DC voltage on OE# and A9 pin is -0.5 V. During voltage transitioning period, OE# and A9 pin may undershoot GND to -2.0 V for a period of time up to 20 ns.
DC AND AC OPERATING RANGE
Part Number Operating Temperature Program/Erase Read V CC V PP V CC Pm37LV512 0C to 70C 2.7 V - 3.6 V 11.5 V - 12.5 V 2.7 V - 3.6 V or 4.5 V - 5.5 V
Programmable Microelectronics Corp.
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Issue Date: Dec, 2002 Rev: 1.3
PMC
DC CHARACTERISTICS
Pm37LV512
Symbol ILI ILO ISB1 ISB2 ICC1 VIL VIH VOL VOH
Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Read Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Condition VIN = 0 V to VCC VI/O = 0 V to VCC CE#, OE# = VCC 0.3 V CE# = VIH to VCC f = 5 MHz; IOUT = 0 mA
Min
Typ
Max 1 1
Units A A A mA mA V V V V
18 0.01 5 -0.5 0.7 VCC
100 3 15 0.8 VCC + 0.3 0.45
IOL = 2.1 mA; VCC = VCC min IOH = -100 A; VCC = VCC min VCC - 0.2
AC CHARACTERISTICS
READ OPERATIONS CHARACTERISTICS
Pm37LV512-70 Symbol tRC tACC tCE tOE tDF tOH tVCS Read Cycle Time Address to Output Delay CE# to Output Delay OE# to Output Delay CE# or OE# to Output High Z Output Hold from OE#, CE# or Address, whichever occured first VCC Set-up Time 0 0 50 Parameter Min 70 70 70 35 20 Max ns ns ns ns ns ns s Units
Programmable Microelectronics Corp.
10
Issue Date: Dec, 2002 Rev: 1.3
PMC
AC CHARACTERISTICS (CONTINUED)
READ OPERATIONS AC WAVEFORMS
Pm37LV512
t RC
ADDRESS ADDRESS VALID
t ACC
CE#
t CE t OE t DF
OE#
WE#
tO H
OUTPUT HIGH Z
OUTPUT VALID
t VCS
VCC
OUTPUT TEST LOAD
3.3 V
INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
1.8 K OUTPUT PIN
3.0 V Input 0.0 V 1.5 V
AC Measurement Level
1.3 K
100 pF
PIN CAPACITANCE ( f = 1 MHz, T = 25C )
Typ CIN COUT 4 8
Max 6 12
Units pF pF
Conditions VIN = 0 V VOUT = 0 V
Note: These parameters are characterized but not 100% tested.
Programmable Microelectronics Corp.
11
Issue Date: Dec, 2002 Rev: 1.3
PMC
AC CHARACTERISTICS (CONTINUED)
WRITE (PROGRAM/ERASE) OPERATIONS CHARACTERISTICS
Pm37LV512
Pm37LV512-70 Symbol tAS tAH tCES tCEH tDS tDH tORT tOES tOEH tPW tEW tRT tART tA9S tA9H Parameter Min Address Set-up Time Address Hold Time CE# Set-up Time CE# Hold Time Data Set-up Time Data Hold Time OE# Rise Time for Program and Erase OE# SetupTime for Program and Erase OE# Hold Time for Program and Erase WE# Program Pulse Width WE# Erase Pulse Width OE#/A9 Recovery Time for Erase A9 Rise Time to 12V during Erase A9 Setup Time during Erase A9 Hold Time during Erase 1 1 1 1 0 30 0 0 40 0 1 1 1 20 100 Max ns ns ns ns ns ns ns ns ns s ms ns ns ms ms Units
Programmable Microelectronics Corp.
12
Issue Date: Dec, 2002 Rev: 1.3
PMC
AC CHARACTERISTICS (CONTINUED)
BYTE PROGRAM OPERATIONS AC WAVEFORMS
tA S
Pm37LV512
ADDRESS
ADDRESS VALID
DATA IN
VH
HIGH-Z tO E S
DATA VALID tD S
// // // // //
tA H
tD H
OE#
V CC V SS
tO R T
tO E H
//
WE# tC E S CE#
tP W
tC E H
//
CHIP ERASE OPERATIONS AC WAVEFORMS
ADDRESS (Except A9)
DATA IN
VH V CC V SS VH V CC V SS
tO E S tO E H tO R T tA 9 S tA R T tA 9 H tR T
OE#
A9
WE# tC E S tE W CE# tC E H
Programmable Microelectronics Corp.
13
Issue Date: Dec, 2002 Rev: 1.3
PMC
AC CHARACTERISTICS (CONTINUED) RELIABILITY CHARACTERISTICS
Parameter Endurance Data Retention ESD - Human Body Model ESD - Machine Model Latch-Up Min 1,000 20 2,000 200 100 + ICC1 Unit Cycles Years Volts Volts mA Test Method
Pm37LV512
JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78
Note: These parameters are characterized but not 100% tested.
Programmable Microelectronics Corp.
14
Issue Date: Dec, 2002 Rev: 1.3
PMC
PACKAGE TYPE INFORMATION 32J
32-Pin Plastic Leaded Chip Carrier Dimensions in Inches (Millimeters)
.485(12.32) .495(12.51)
Pm37LV512
.447(11.35) .453(11.51)
.009 .015 025(.635)X30
.585(14.86) .595(15.11) Pin 1 I.D. .547(13.89) .553(14.05)
.123(3.12) .140(3.56) .076(1.93) .095(2.41)
SEATING PLANE
.400 REF. .510(12.95) .530(13.46) .013(.33) .021(.53)
.026(.66) .032(.81)
.050 REF.
32P
32-Pin Plastic DIP Dimensions in Inches (Millimeters)
1.640(41.7) 1.680(42.7) 32 17 .537(13.64) .557(14.05) Pin 1 I.D. 16 .005(.127) MIN
0 10 .008(0.20) .013(0.33) .625(15.88) .665(16.89) .600(15.24) .625(15.88)
.040(1.02) .065(1.65)
.146(3.71) .162(4.11)
SEATING PLANE .120(3.05) .160(4.07) .090(2.29) .110(2.79) .014(.36) .022(.56)
.015(.38) MIN
Programmable Microelectronics Corp.
15
Issue Date: Dec, 2002 Rev: 1.3
PMC
Pm37LV512
PACKAGE TYPE INFORMATION (CONTINUED) 32V
32-Pin Thin Small Outline Package (TSOP 8mm x 14mm)(Millimeters)
Pin 1 I.D.
.037(.95) .041(1.05 .006(.16) .011(,27) .315(7.90) .319(8.10) .020(0.05) BSC .020(.05) .006(.15)
.484(12.30) .492(12.50) .543(13.80) .560(14.20)
.047(1.20) MAX .010(.25) 0 5
.004(.10) .008(.20)
.020(.50) .028(.70)
Programmable Microelectronics Corp.
16
Issue Date: Dec, 2002 Rev: 1.3
PMC
REVISION HISTORY
Date March, 2002 Revision No. Description of Changes 1.0 New publication Revised features and general description Removed 90 ns speed grade Revised bus operation modes May, 2002 1.1 Revised absolute maximum ratings Revised ISB1 specification
Pm37LV512
P ag e N o . All 1 3, 10, 12 6 9
10 12, 13 2 7 1, 2, 3, 16
Revised program/erase operation characteristics and waveforms Corrected the typo in 32-Pin PDIP pin connection June, 2002 1.2 Corrected the typo of TRT recovery time in Byte Programming Flowchart D e c. 2 0 0 2 1.3 Added 32-Pin VSOP package spec.
Programmable Microelectronics Corp.
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Issue Date: Dec, 2002 Rev: 1.3

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